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Paper Details

FPGA Implementation of Successive Cancellation Polar Decoder Architecture

R.Sornalatha , A.Muthumanicckam, L.Vijayprabakaran

Journal Title:INTERNATIONAL JOURNAL OF ADVANCED RESEARCH TRENDS IN ENGINEERING AND TECHNOLOGY
Abstract


Nowadays polar codes are becoming one of the most favourable capacity achieving Error Correction Codes (ECC) for their simple low encoding and decoding complexity, have received much attention in recent years; they probably achieve the theoretical capacity of discrete memoryless channels using the low complexity successive cancellation (SC) decoding algorithm. However, among the very few prior successive cancellation polar decoder designs, the required long code length makes the decoding latency high. As a new polar decoder, referred to as 2b-SC-Precomputation decoder, reduce the latency from (2n-1) to ((3n/4)-1) without performance loss. Furthermore, in our method, the decoding latency decreases rapidly with increasing throughput. Significant latency and throughput reductions are shown by simulation results and also report synthesis results for ASIC.

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