• We are available for your help 24/7
  • Email: info@isindexing.com, submission@isindexing.com


Paper Details

SRAM Performance Enhancement Using Sense Amplifier Based Design Technique

K. Ramesh, A.Manonmani , M.Gomathi , V.Lawanya

Journal Title:INTERNATIONAL JOURNAL OF ADVANCED RESEARCH TRENDS IN ENGINEERING AND TECHNOLOGY
Abstract


SRAM cells are known to be highly sensitive to process variations due to the extremely small device sizes. Local random variations in device characteristics can easily lead to Read disturb, Write failure, or Read access failure in SRAM cell. Transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without any on-chip or offchip negative voltage source. In this work Read assist sense amplifier based design technique is presented to reduce read failure of SRAM cell. Furthermore, false read before write operation, common to conventional 6T designs due to bitselect and word line timing mismatch, is eliminated using the Read assist sense amplifier based design technique. Tran- NBL able to achieve higher reduction in write failure compared to lower cell supply voltage while preserving the benefits of bit-line based control and eliminating the need for additional voltages. The design of Transient Negative Bit Line Voltage Scheme and sense amplifier based design technique for 6T SRAM has been implemented and corresponding result was obtained using DSCH tool. Simulation analysis of the proposed SRAM design with state-of-art designs demonstrates show better performance in terms of area power and delay.

Download