A High Speed and Area Efficient Wallace Tree Multiplier with Booth Recoded Technique?
B. Venkata Sateesh, Shiju C Chacko?
Journal Title:International Journal of Computer Science and Mobile Computing - IJCSMC
Wallace tree is an improved version of tree based multiplier architecture.wallace tree multiplier implemented by using booth recoder in this paper. This paper aims reduction of additional latency and area of improved version of Wallace tree multiplier. In proposed method implementing by the use of booth algorithm to generate partial products and compressor adder techniques can be used to sum partial products. The modified architecture shows result of proposed architecture is around 67 Percent faster than the existing Wallace-tree multiplier, 22 percent faster than the radix-8 Booth multiplier, 18 Percent faster than the radix-16 Booth multiplier. Proposed architecture shows better performance in terms of area and speed.