Design of Moderate Speed and Moderate Resolution Successive Approximation Analog to Digital Converter?
Mr. Jitendra Waghmare?, Prof. P.M. Ghutke?
Journal Title:International Journal of Computer Science and Mobile Computing - IJCSMC
This Paper presents the Design of analog to digital converter (ADC) for low power applications, so here is the selection of right architecture is very crucial. We have chosen successive approximation Analog to Digital Converter because of their compact circuitry as compared with the Flash ADC which makes this SAR ADC inexpensive. Day By Day more and more applications are built on the basis of power consumption so this SAR ADC will be useful for high speed with medium resolution and low power consumption. The Successive Approximation (SAR) architecture is very suitable for data acquisition, it has resolutions ranging from 8 bits to 12 bits and sampling rates ranging from 50 KHz to 50 MHz